The present invention relates to minimizing power loss associated with the dead time of switching power supplies.
In U.S. patent application Ser. No. 11/058,969, filed Feb. 16, 2005, the entire disclosure of which is incorporated by reference herein, a method and apparatus for minimizing the power loss associated with the dead time of switching power supplies is described. In a switching power supply, for example, a switching converter, two control switches are typically employed, one of which operates as a synchronous rectifier. The two switches are generally controlled so that both switches are never on at the same time. A “dead time” is provided between the on-times of the two switches to prevent cross conduction across the DC voltage supply between which the two switches are connected in series.
In the prior patent application, a method is described in which a selected parameter associated with the power loss during the dead time is monitored. The selected parameter may be the duty cycle of a pulse width modulated (PWM) control signal adapted to drive a control terminal of at least one of the switches or the error signal from an error amplifier driving the PWM modulator, as disclosed in FIG. 1A of related U.S. Pat. No. 7,098,640. The entire disclosure of this patent is also incorporated by reference herein. In the system described, the control arrangement for the switches continually changes the dead time from a first dead time to a second dead time and compares the selected parameters and thus power losses for the first and second dead times and determines which of the power losses associated with the two dead times is smaller. A dead time implementing stage implements the two dead times and the control arrangement selects the dead time associated with the smaller power loss and provides a signal to the dead time implementing stage to set the selected dead time.
A fundamental element of a successful power loss minimizing dead time (PLMDT) scheme is to find the dead time corresponding to the minimum power loss. The approach described above basically modulates the efficiency of the synchronous power converter with the change in dead time and then synchronously demodulates the results for processing to make decisions about which dead time is best. Several practical limitations impede this process by effectively producing a “noise” which must be overcome for the power loss minimizing dead time (PLMDT) algorithm to operate successfully. These practical limitations include:
Instrumentation Errors
For an analog signal processing scheme, the offset errors of any amplifiers and comparators must be overcome by any differences in the acquired signal which are caused by power loss. Since the signal size can be in the mV range, it is evident that offsets of 1 mv or lower are desirable. In the PLMDT scheme, a sample and hold (S&H) circuit may be used together with a comparator to store the prior power loss sample and the present one and compare the two to determine which is “better”, or which represents a lower power loss. For economic reasons it is desirable for the sample and hold (S&H) capacitor of the S&H module to be tied to the power loss decision comparator input. In the case of a S&H circuit, low input bias and offset current are desirable. Low input bias/offset currents and low input offset voltage are conflicting requirements that can make this circuit difficult to implement in an economical way.
Local Power Loss Minima
The response of power loss as a function of dead time is not necessarily monotonic over the full range of the dead time modulator. This can cause some implementations to get trapped at sub-optimum dead times, sometimes far away from the optimum dead time.
Transient Loads
During steady state load conditions, all the changes in power loss are a function of PLMDT operation at its sample frequency of change. When the load varies, this variation gets superimposed on the modulation caused by the deliberate changing of dead time. If the load varies in a very random way, simple averaging can eliminate this undesirable signal, even if it is large (often the case). If the load varies in a coherent manner, however, this “false” signal can overwhelm the desired signal if its frequency is near the PLMDT sample frequency or harmonic/sub-harmonic. This can cause erratic or even destructive operation.